This invention relates to a framing circuit for a digital receiver, and more particularly to a circuit arrangement for finding a frame bit which occurs in every frame or alternate frame to synchronize a data receiver, and to maintain it in synchronization.
In digital transmission systems, particularly carrier systems for sending voice signals in digital format, the data bits are transmitted in cyclically recurring frames. There are usually a number of channels, each having a recurring time slot in each frame. One such system is known as Tl carrier, which may have either type D1 or Type D2 channel banks in the multiplexing equipment.
When looking at a data stream, one bit pretty much looks like any other. The purpose of framing is to establish a time reference so that the data can be identified and properly routed or decoded. The data is usually organized into fixed blocks and the blocks are usually separated by a framing bit. In Tl D1 format, the data block is organized as 24 channels of 8 bits each which results in 192 bits. One framing bit is added giving a total of 193 bits.
The frame bit is identified by following a distinctive sequence that is not likely to occur for any long period of time in the data stream. In normal operation, when the circuit is in frame, no data sequence can disrupt the framing. The framing circuit looks only at the framing bits and not at the data. If substantial deviation from the framing sequence occurs, then a misframe is declared and a frame search starts. Only then does the framing circuit look at the data. This is when the framing circuit is vulnerable to data sequences that look like framing. Such a pattern would not be expected to persist indefinitely and and so a frame search would eventually be reinitiated. The search is systematic through all 193 bit positions and correct framing is declared only when sufficient confidence is achieved that the sequence is true framing and not just a similar data pattern. Some error tolerance is allowed in the normal mode so that random bit errors do not cause a misframe. No error tolerance is allowed during the search mode.
The D1 framing sequence consists of the alternating patter . . . 010101 . . . . If a variation from this pattern occurs then it is referred to as a "violation". The normal mode consists of counting the 193 bits of the frame and checking for a framing violation. If a violation occurs, then that violation is registered in some sort of decaying memory device and a check is made to see if a preset threshold is exceeded. If the threshold is not exceeded, then the framing circuit continues to the next frame. If enough violations occur in close succession, the threshold is exceeded and a misframe is declared and a framing search is initiated. When the search mode is started, the frame counter slips 1 bit before resuming its count. At the end of the 193 count, a check is made to see if there is a violation. If there is a violation, then the search process is reinitiated immediately. If no violation occurs, then there is a possibility that the framing is correct. In this case, a memory device is incremented and a check is made to determine if enough consecutive non-violations have occurred to declare a correct frame. If not, then the next frame is examined to see if the pattern still persists. If enough consecutive non-violations occur, then confidence is high that the correct framing has been detected. A true frame is declared returning the framing circuit to the normal mode. The monitor for non-violations in the search mode is referred to as a "confidence circuit". Any violation during the search mode wipes out confidence in that position being correct. Random data could look like framing for a short period of time. The confidence circuit is necessary to insure that the probability of data looking like framing is sufficiently small that a correct frame can be declared and a return to the normal mode can be accomplished.
The violation monitoring is done in the D1 channel bank by pulsing a leaky capacitor. Every time a violation occurs, the voltage on the capacitor is increased by a fixed amount. The charge will eventually leak off, but enough violations in a short period of time will generate enough voltage on the capacitor so that the threshold is reached and a misframe is declared. The exact values of the components are not critical. The threshold may be reached when the three consecutive framing bits are in violation or when approximately three out of five consecutive framing bits are in violation. For the D2 channel bank, about four closely spaced violations are necessary to cause misframe.
The main difference in D2 framing is that the framing bit appears only in the 193rd position in alternate frames while the other 193rd bit is used for other things such as identifying signaling frames or carrying common channel signaling. The framing bit alternates just as in D1. The resulting sequence in the 193rd bit position is . . . 0x1x0x1x0x1x . . . where x can be anything except the alternating sequence. As far as the reframe circuit is concerned, the frame is length 386 instead of 193 and every 386th bit is a framing bit following the same pattern as D1. The difficulty arises from the fact that if the D2 reframe circuit is used the reframe time is four times as long as D1. This fact comes from the rule that reframe time is proportional to the square of the frame length.
In order to speed up the D2 reframe process, 8 bits are examined at a time. The first of the 8 bits is considered to be the prime candidate and the others are considered in succession. As long as the first bit follows the correct pattern, then no action is taken until a confidence counter reaches a threshold which says that sufficient confidence in the prime candidate has been attained so that a true frame can be declared. During the time that the candidate is being considered, a history of past violations is being accumulated on the other 7 bits. In the event that the candidate fails, the second bit can be examined with a past history that indicates whether or not it should be considered. If there have been any violations in that position since the frame search began, then the second bit is immediately eliminated from contention and the third bit is examined in the same manner. This process continues until a contender is found or else all 8 bits are exhausted. Whenever a contender is found, then it is declared to be the new prime candidate and the confidence counter is restarted from zero. In this manner, up to eight non-framing positions cn be eliminated at a time rather than having to examine each position individually. Bits which are not frame bits can be skipped over fairly rapidly so that the total reframe time is improved considerably. In fact, the D2 channel bank reframes a little faster than D1. The normal mode of the Bell System D2 channel bank has approximately the same error tolerance and misframe method as D1.
Other framing patterns and circuits are also known. See for example U.S. Pat. No. 3,585,306 by F. E. Battocletti, Columns 5 - 7.